1. Field of the Invention
The present invention relates to a logic simulator for verifying the presence of an undesired current generated in a logic circuit.
2. Description of the Background Art
FIG. 7 is a block diagram of a conventional logic simulator for logically verifying the operation of a logic circuit. A circuit connection data portion 7 receives a logic circuit data D1 that is drawing data of the circuit to be simulated to output a circuit connection data D2 specifying the connection of devices forming the logic circuit to a logic circuit verifying portion 6 as a function of the logic circuit data D1. A logic verification node condition portion 8 outputs to the logic circuit verifying portion 6 a logic verification node condition data D3 specifying the conditions of nodes to be logically verified among those provided between the devices specified by the circuit connection data D2.
The logic circuit verifying; portion 6 carries out a logic simulation as a function of the circuit connection data D2 to output signals (logic verification signals) only provided from the nodes satisfying the conditions specified by the logic verification node condition data D3 as a logic simulation result D4 to a logic verification result output portion 9. The logic verification result output portion 9 outputs a logic simulation result list D5 in which the results are described in a list form as shown in FIG. 8 as a function of the logic simulation result D4. In FIG. 8, reference numeral 51 designates logic verification signal names; 52 designates a time change of a time unit that is a simulation execution time; and 53 designates logical results at the simulation execution time. The logical results 53 include four signals: 0, 1, X (indeterminate level) and Z (floating state).
In the conventional logic simulator formed as above-described, the logic simulation results of the signals provided from the nodes satisfying the conditions specified by the logic verification node condition data D3 are outputted finally as the logic simulation result list D5.
For detection of an abnormal current such as a through current generated in the logic circuit, it is necessary to pay attention to the floating state of the node. The only method for detecting the abnormal current such as the through current by the conventional logic simulator is to carry out the logic simulation in the logic circuit verifying portion 6, with all of the nodes between the devices specified by the circuit connection data D2 taken as logic verification target nodes, so that an expert observes the logic simulation result list D5.
However, the logic simulation result list D5 outputted as a function of the logic simulation result D4 provided that all of the nodes are the logic verification target nodes includes the logic verification results for an enormous number of signals. It is impracticable to observe such logic simulation result list D5 to detect the abnormal current such as the through current. In addition, a memory capacitance for storing the logic simulation result D4 having the enormous data is far increased.